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ArchAgent v2: A Case Study with the Data Prefetchin... | AI Research

Key Takeaways

ArchAgent v2 is a framework designed to automate the discovery of multi-level computer microarchitecture, specifically focusing on data prefetching.
In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching.
While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger.
Our discovered policy achieves a 3.8\% geometric mean IPC speedup over the baseline overall and a 0.3\% improvement over the prior champion, BertiGO.
On low-bandwidth single-core configurations, our policy yields a 4.6\% performance speedup compared to only 2.6\% for BertiGO.

Paper AbstractExpand

Agentic artificial intelligence has shown great promise in automating algorithm design, but scaling similar techniques to computer microarchitecture discovery remains challenging due to vast search spaces, strict hardware budgets, and long simulation times. In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching. While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger. To overcome this, we introduce two new additions to ArchAgent: a cascaded evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at individual cache levels, and a hardware-realizability feedback loop that embeds real-time size-estimation directly into the evolution process. Evaluated under identical rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 automatically designs a three-level prefetcher that outperforms the winning hand-designed solution, further demonstrating automated agentic discovery as a useful tool for computer architects. Our discovered policy achieves a 3.8\% geometric mean IPC speedup over the baseline overall and a 0.3\% improvement over the prior champion, BertiGO. On low-bandwidth single-core configurations, our policy yields a 4.6\% performance speedup compared to only 2.6\% for BertiGO. However, multi-core evolution still remains a significant challenge due to simulation latency impeding evolution speed. Finally, our profiling of an ArchAgent evolution of over 12,000 candidate designs provides key insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.

ArchAgent v2 is a framework designed to automate the discovery of multi-level computer microarchitecture, specifically focusing on data prefetching. While previous agentic AI systems successfully optimized single-level cache replacement, they struggled to scale to the complex, multi-level prefetching required by modern hardware. ArchAgent v2 addresses these challenges by using an evolutionary search process to design prefetchers that operate across L1D, L2, and LLC cache levels simultaneously.

Scaling Microarchitecture Discovery

The primary challenge in automating microarchitecture design is the vast search space and the need to adhere to strict hardware constraints. ArchAgent v2 introduces two key methodological changes to manage this complexity:

Cascaded Evolutionary Search: Instead of evolving all prefetchers at once, the framework uses a "divide-and-conquer" approach. It sequentially evolves and freezes prefetchers at each cache level (L1D, then L2, then LLC) before conducting a final global optimization. This reduces the search space and prevents performance improvements at one level from invalidating gains at another.
Hardware-Realizability Feedback Loop: To ensure designs are physically viable, the framework includes an automated interface that calculates the storage footprint of each proposed prefetcher. If a design exceeds the specific storage budget for a cache level (e.g., 32KB for L1D), it is rejected during the compilation phase.

Performance Results

Evaluated under the rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 produced a three-level prefetcher that outperformed the championship-winning, hand-designed policy, BertiGO.
The ArchAgent v2 policy achieved a 3.8% geometric mean IPC (instructions per cycle) speedup over the baseline. Compared to BertiGO, it provided a 0.3% improvement overall. In low-bandwidth single-core configurations, where cache pollution and bus contention are significant, the ArchAgent v2 policy yielded a 4.6% speedup, compared to 2.6% for BertiGO.

Limitations and Insights

Despite these gains, the research notes that multi-core evolution remains a significant hurdle. Multi-core configurations introduce high simulation latencies, which slow down the evolutionary process and increase the complexity of the search space. Consequently, the discovered policies showed limited gains in multi-core settings compared to their performance in single-core environments.
By profiling over 12,000 candidate designs, the researchers identified that successful architectural breakthroughs often rely on a combination of major shifts followed by minor refinements. The winning design specifically succeeded by dynamically scaling prefetch lookahead, throttling bandwidth based on core and memory signals, and arbitrating between different memory streams. This suggests that automated evolutionary agents can effectively synthesize complex logic when provided with structured feedback and a partitioned search strategy.

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