The PCBRouteAgent paper tests whether a multimodal agent can guide routing on a printed circuit board. It divides the job between a planner that decides how connections should cross the board and an executor that turns those decisions into traces through KiCad. The preprint was submitted to arXiv on November 5, 2026.
How the routing is split
The Global Routing Planner sees a board image and structured electrical and geometric information. It specifies the topology, order, corridors and layer transitions for connections. The Detailed Routing Executor realizes the guides with KiCad’s native routing engine. It can try limited local recovery when the original guide leaves a route unresolved.
Failures that remain are returned as structured feedback. The planner can revise the affected guides while preserving routes already accepted. That separation matters when changing one connection could otherwise undo a larger part of the layout.
Where it passed cleanly
The authors tested 247 synthetic and real-world boards across four PCBWorld-Bench splits. They report clean-pass rates of 100% on D2, 94.9% on D3-A, 100% on D3-B and 40% on D3-C. On the three real-world subsets the clean-pass rate exceeded the strongest evaluated baseline by 13.9, 36 and 10 percentage points, respectively.
What the lowest split shows
The 40% result on D3-C is useful context for the higher scores elsewhere. The agent can produce complete routes on many test boards, while its hardest reported split still leaves most boards outside the clean-pass result. The paper gives PCB engineers a way to evaluate a planning assistant while keeping the routing engine and design rules in the loop. To compare it with another system, use the split-level results and the same definition of a clean pass rather than combining results from boards of different difficulty.
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